The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Authors: Kazutomo Yoshii (Argonne National Laboratory (ANL)), John Shalf (Lawrence Berkeley National Laboratory (LBNL)), Kentaro Sano (RIKEN Center for Computational Science (R-CCS))
Abstract: As demand for architectural innovation accelerates in the post-Moore era of HPC and scientific edge computing, the importance of accessible and scalable design methodologies has never been greater. This BoF will focus on the critical role of open-source hardware tools in advancing research and accelerating chip prototyping. Modern chip development increasingly relies on large-scale computing for simulation, formal verification, power–performance–area analysis, and physical layout. These workflows not only require substantial computational resources but also create opportunities to integrate HPC and AI into design processes in transformative ways. Open-source tools provide a unique opportunity to lower barriers to entry, enable reproducibility, and foster innovation across diverse communities.
The session invites contributions from both hardware and software communities, spanning circuit-level abstractions, design-space exploration, and scalable toolchains. Special invited speakers include Mark Ren (NVIDIA, U.S.), Lilia Zaourar (CEA, Europe), and Toru Niina (RIKEN, Japan), representing global perspectives from industry, national laboratories, and academia. Their talks will highlight international efforts that demonstrate the power of open-source methodologies to accelerate chip design and strengthen collaboration across regions.
To maximize interaction, this BoF will include impromptu pitches from attendees and an open Q&A discussion. This is not just a listening session—it is an opportunity for participants to co-create future directions, exchange ideas, and form new collaborations. We encourage all attendees to be actively involved in shaping the outcomes.
Expected results include actionable insights, new collaborations across traditionally separate communities, and concrete follow-up efforts to advance open, reproducible, and scalable hardware design.
Long Description: As the HPC and scientific edge computing landscape evolves beyond Moore's Law, there is a growing need for architecture innovation and agile design methodologies to sustain performance and energy efficiency. This Birds-of-a-Feather (BoF) session will highlight the critical role of open-source hardware tools in advancing architecture research and accelerating chip prototyping, with an additional focus on how these tools enable experimentation with HPC- or AI-assisted workflows throughout the chip development process.
Modern chip design increasingly requires significant computing power for tasks such as simulation, formal verification, power-performance-area (PPA) estimation, layout, and multiphysics analysis. These compute-intensive processes position chip development as a natural HPC workload and a promising target for AI acceleration -- forming the basis for an emerging HPC/AI-accelerated chip design flow. Open-source tools provide a unique platform for researchers and practitioners to experiment with novel flows, integrate custom components, and iterate quickly, often in ways that are impractical with commercial tools.
The goals of this BoF are to foster collaboration among professionals working in architecture design and prototyping, highlight emerging trends and challenges in the adoption of open-source hardware tools, and explore how HPC and AI can be leveraged to accelerate the design process. We also aim to build a sustained network of practitioners who can share knowledge, coordinate efforts, and launch future initiatives.
The session will feature community-driven discussions on architecture research in HPC, practical experiences using open-source hardware tools, and a gap analysis to identify unmet needs. Topics of interest include the integration of open-source electronic design automation (EDA) tools, scalable architecture simulation frameworks, AI-augmented design automation, domain-specific accelerators for scientific computing, and chiplet-based methodologies for low-cost prototyping and integration.
This BoF is highly relevant to the HPC community. It brings together stakeholders from hardware architecture, system simulation, software tooling, and design automation to address a critical question: how can we design next-generation chips faster and more efficiently using the capabilities of HPC itself? Despite growing momentum, open-source hardware tools are still underutilized in HPC. Meanwhile, the chip design workflow itself is becoming increasingly aligned with traditional HPC workloads, offering new opportunities for collaboration across communities.
We previously organized a BoF on this topic at SC24, which attracted around 30 participants. That session featured open-floor elevator pitches and several impromptu talks. For SC25, we aim to broaden the scope and improve structure. The updated session will feature brief invited remarks to seed discussion, better time allocation for participant input, and deeper focus on HPC/AI-accelerated chip design flows.
Participants will gain exposure to the chip development workflow, learn about current trends and tools, share ideas and challenges, and take first steps toward engaging with open, high-productivity hardware design in the HPC context.
Website: https://sites.google.com/view/sc25archpro/home