The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Authors: Anil Godbole (Intel), Kurtis Bowman (Advanced Micro Devices, Inc. (AMD)), Luis Ancajas (Micron Technology), Yongjin Cho (Panmnesia), Ronen Hyatt (UnifabriX)
Abstract: As AI and HPC workloads scale, traditional architecture faces critical memory and bandwidth limitations. Compute Express Link® (CXL®) offers a transformative solution, enabling low-latency, coherent communication across CPUs, GPUs, and memory devices. This session will explore how CXL 2.0 and 3.x support memory disaggregation and composable infrastructure to unlock scalable and flexible deployment of large models and simulations. Attendees will learn how memory pooling and sharing reduce overprovisioning, improve utilization, and lower costs. We invite system architects, researchers, hardware developers, and operators to discuss real-world CXL adoption, implementation challenges, and opportunities to reshape the next-generation AI and HPC systems.
Long Description: Modern AI and HPC workloads are pushing traditional system architecture to its limits. Training Large Language Models (LLMs), running real-time inference pipelines, and simulating complex physical systems all require massive memory capacity, high bandwidth, and low latency across heterogeneous compute environments. Systems are currently struggling to achieve maximum performance due to the limited local memory per CPU or accelerator, inefficient memory utilization, and rigid hardware coupling that restricts scalability and flexibility.
AI models are outpacing memory capacity, often requiring terabytes of memory and leading to costly overprovisioning of compute as a workaround. In HPC, increasingly data-intensive simulations demand high-speed memory access across nodes and accelerators, causing bottlenecks, underutilized memory, and rising infrastructure costs.
Compute Express Link® (CXL®) is an open standard for high-speed, low-latency interconnects. CXL enables coherent memory sharing between CPUs, GPUs, FPGAs, memory expanders, and other accelerators. Of particular significance is CXL memory pooling and sharing, which decouples memory from compute, allowing multiple hosts and devices to dynamically access a shared pool of memory.
This memory disaggregation unlocks several key benefits:
• Scalability: Systems can scale memory independently of compute, enabling organizations to support larger AI models and simulations without redesigning entire nodes.
• Efficiency: Memory pooling eliminates the problem of stranded or underutilized memory. Instead of locking memory to individual devices, CXL enables dynamic allocation based on workload demands.
• Flexibility: CXL supports composable infrastructure, where compute, memory, and acceleration resources can be provisioned on demand.
• Lower TCO: By reducing overprovisioning and maximizing memory utilization, CXL helps control power, cooling, and hardware costs.
• Minimized Performance Overhead: By guaranteeing cache coherency in hardware, CXL minimizes inter-device communication overhead compared to conventional disaggregation approaches.
This session will bring together CXL members – actively working and implementing CXL solutions today – to explore how CXL memory pooling and sharing can help overcome AI and HPC architectural constraints. The presentation will also discuss real-world use cases, deployment experience (success & challenges), and workload and benchmark results of CXL technology. The goal of the session is to foster collaboration around CXL technology and best practices for deployment.
The learning objectives for this session include:
• Understand the limitations of traditional memory architectures in AI and HPC environments, including bottlenecks caused by fixed, local memory and inefficient resource utilization.
• Explain how CXL enables memory pooling and sharing between CPUs, accelerators, and memory expanders, and why this architecture is particularly beneficial for memory-intensive workloads.
• Evaluate real-world AI and HPC use cases that benefit from CXL technology, including LLM training, RAG/agentic AI, graph database, big data analysis, parallel computing, and composable infrastructure designs.
• Recognize the implementation challenges involved in deploying CXL-enabled infrastructure, including software support, orchestration, and memory management.
• Explore future memory-centric system designs and how the SC community can contribute to standardization, testing, and adoption of CXL in next-generation systems.