Panels Archive

CPUs Have a Memory Problem: The Difficulty of Designing CPU-Based HPC Systems with Very High Memory Bandwidth

Moderator: Joe Greenseid (Microsoft Azure)
Panelists: Galen Shipman (Los Alamos National Laboratory (LANL)), Heidi Poxon (NVIDIA Corporation), Nuwan Jayasena (Advanced Micro Devices, Inc. (AMD)), Thomas Metzger (Intel Corporation), Filippo Spiga (NVIDIA Corporation)

Abstract: Many HPC applications are to some degree or another memory bandwidth-bound. However, for applications that run on CPUs, it has been difficult to balance the tradeoffs of bandwidth, latency, capacity, and power to achieve a big win in improved memory bandwidth. Often, to get more bandwidth, it requires an imbalance in other areas such as excess capacity, worse latency, or increased power to the CPU and/or the memory. In this session, our panel of experts—including silicon designers, system architects, scientific computing experts, and hyperscalar system providers—will examine the problems that we have seen in the past and present in trying to design platforms around CPUs and memory technologies that are not being designed to work optimally together and what options and opportunities we in the community have to improve the situation with both hardware and software choices we can make.

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