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An Approach to Identify Divergences in Hardware Designs for HPC Workloads

Workshop: 11th International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC 2025)

Authors: Doru Thom Popovici (Lawrence Berkeley National Laboratory), Mario Vega and Angelos Ioannou (Lawrence Berkeley National Laboratory (LBNL)), Fabien Chaix (Foundation for Research and Technology - Hellas), Dania Mosuli and Blair Reasoner (University of Houston Clear Lake), Tan Nguyen (Lawrence Berkeley National Laboratory (LBNL)), Xiaokun Yang (University of Houston Clear Lake), and John Shalf (Lawrence Berkeley National Laboratory (LBNL))

Abstract: Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has traditionally been a labor-intensive task. Accelerator development typically requires low-level programming in Verilog alongside significant manual optimization effort. Recently, to alleviate this challenge, high-level hardware design tools like Chisel and High-Level Synthesis have emerged. However, as with any compiler, some of the generated Verilog may be suboptimal compared to expert-crafted designs. Understanding where these inefficiencies arise is crucial, as it provides valuable insights for both users and tool developers. In this paper, we propose a methodology to hierarchically decompose mathematical kernels—such as Fourier transforms, matrix multiplication, and QR factorization—into a set of common building blocks/primitives. Then the primitives are implemented in the different programming environments, and the larger algorithms get assembled. Furthermore, we employ an automatic approach to investigate the achievable frequency and required resources at each level identifying key locations where designs may deviate

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