The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop: IA^3 2025 — 15th Workshop on Irregular Applications: Architectures and Algorithms
Authors: Takaaki Miyajima and Leon Fukuoka (Meiji University)
Abstract: Cerebras CS-2 system is gathering attention to utilise it for scientific applications. The Cerebras CS-2 comes with the world's largest chip, the wafer-scale engine 2 (WSE-2). The WSE-2 has new characteristics that distinguish it from other computers, such as a massive number of small processing elements, low-latency 2D mesh topology, and a unique distributed memory architecture. By understanding this unique architecture, scientific applications can be accelerated significantly. However, its sustained performance and characteristics have not yet been fully understood. In this study, we give a benchmark study focusing on WSE-2. The objective is to examine the various performance characteristics of WSE-2 in detail, including inter-PE communication. In this paper, benchmarks of the effective computational performance and memory bandwidth are conducted, the Byte/Flop value is calculated, and a roofline model for the WSE-2 is built. Additionally, the effective communication latency of two distinct PEs and the bi-section bandwidth are measured.
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