The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop: LLVM-HPC2025: The 11th Workshop on the LLVM Compiler Infrastructure in HPC
Authors: Konstantinos Sotiropoulos (Chalmers University of Technology, University of Gothenburg); Jonas Skeppstedt (Lund University); and Per Stenström (Chalmers University of Technology, University of Gothenburg)
Abstract: Sparse tensor computations suffer from irregular memory access patterns that degrade cache performance.
While software prefetching can mitigate this, existing compiler approaches lack the semantic insight needed for effective optimization.
We present \textbf{ASaP}, an automatic software prefetching framework integrated within MLIR's sparse tensor dialect.
By leveraging semantic information—tensor formats and loop structure—available during sparsification,
ASaP determines accurate buffer bounds and injects prefetches in both innermost and outer loops, achieving broader coverage than prior work.
Evaluated on SuiteSparse matrices, ASaP demonstrates significant performance gains for unstructured matrices.
For SpMV with innermost-loop prefetching, ASaP achieves 1.38× speedup over Ainsworth \& Jones.
For SpMM with outer-loop prefetching, ASaP achieves 1.28× speedup while Ainsworth \& Jones fails to generate prefetches.
Our experiments reveal that disabling inaccurate hardware prefetchers frees critical resources for software prefetching,
suggesting future architectures should expose prefetcher control as an optimization interface.
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