Workshops Archive

Experiences of Porting Structured and Unstructured Stencil Applications to FPGA using SYCL

Workshop: PMBS25: The 16th International Workshop on Performance Modeling, Benchmarking, and Simulation of High-Performance Computer Systems

Authors: Zadok Storkey, Steven Wright, and Ian Gray (University of York, England)

Abstract: In this paper we explore a stencil application written in SYCL on both CPU and FPGA architectures. We prepare two versions of the application, using a structured grid and an unstructured grid, and then optimise these implementations for CPU and FPGA architectures, with a focus on maintaining portability between both. We benchmark the application on an AMD CPU and an Intel Stratix 10 FPGA, seeking to answer whether we can target FPGAs productively from a single-source code base. Our findings indicate that for low arithmetic intensity kernels FPGA performance is lacking compared to CPU performance, suggesting that FPGA architectures may be unsuitable for such kernels, or that significant platform-specific optimisations may be required to reduce the performance gap, at the expense of developer productivity.

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