Workshops Archive

Assessing a RISC-V Accelerator for Cross-Section Lookup in Chipyard

Workshop: International Workshop on RISC-V for HPC (RISCVHPC)

Authors: Andrew Ledbetter, Kazutomo Yoshii, and John Tramm (Argonne National Laboratory (ANL))

Abstract: High-fidelity nuclear reactor simulations using Monte Carlo neutron transport face bottlenecks in neutron cross-section lookups. We designed a custom RISC-V accelerator for RSBench, integrated with a RocketCore in Chipyard. The pipelined design employs Humlíček’s 8th-order rational ap- proximation to efficiently compute the Faddeeva function during Doppler broadening of multipole cross section data, which forms the inner loop of the program, achieving a 17× cycle reduction for Faddeeva computations and 34.2× for the loop compared to RISC-V software, with similar gains over Intel Core i5 Tiger Lake-U, yielding a 10× wall-clock time improvement. Chipyard’s software-based environment benefits the HPC community by enabling accelerator eval- uation. These results highlight RISC-V’s potential for HPC through custom accelerators and code portability. Future work will optimize operating frequency and extend to additional simulation kernels.

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