Workshops Archive

Simulating Hybrid Analog + RISC-V Systems for HPC Applications

Workshop: International Workshop on RISC-V for HPC (RISCVHPC)

Authors: Cameron Durbin (University of Oregon), Jacob Flores (Sandia National Laboratories), Thomas Weatherly (Georgia Tech Research Institute), and Ben Feinberg (Sandia National Laboratories)

Abstract: As digital scaling trends have slowed over the past decade, there has been renewed interest in new computing paradigms such as analog. Analog computing has the potential to provide performance and efficiency beyond what is achievable by digital systems; however, many challenges remain. One such challenge is supporting complex applications using analog components that implement few computational kernels. We consider on a class of hybrid analog + digital systems where analog accelerators are used as tightly integrated coprocessors within each core. The RISC-V ISA simplifies the design of hybrid systems, providing a mature software stack for the digital components allowing system designers to focus on the analog-specific aspects of the architecture and software. To investigate the viability of these architectures for high performance computing we evaluate two iterative linear solvers using hybrid analog + RISC-V processors using the Structural Simulation Toolkit.

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