Research and ACM SRC Posters Archive

The Impact of Maximum Vector Length on Cache Management Techniques in RISC-V Vector Extension

Poster Type: Research Posters

Author: Shunya Nomura (Tohoku University), Jiaheng Liu (RIKEN Center for Computational Science (R-CCS)), Keichi Takahashi (The University of Osaka, Tohoku University), Hiroyuki Takizawa (Tohoku University)

Supervisor:

Abstract: In recent years, the RISC-V vector extension (RVV) has attracted increasing attention. The RVV allows programs to be executed on processors with various maximum vector lengths (MVLs). Consequently, even when running the same program, the memory access pattern may vary depending on the MVL of the processor, potentially leading to changes in the optimal cache management technique. In this poster, we focus on replacement policies and the use of non-temporal hints. We execute the same program on processors with different MVLs and compare multiple cache management techniques. The results demonstrate that the optimal cache management technique can vary with the MVL. This finding highlights the necessity of selecting cache management techniques while taking the MVL into account when utilizing RVV. In the poster session, we will explain these research findings using charts that illustrate the performance results.

Best Poster Finalist (BP): no
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